Selectively doped trench device isolation

ABSTRACT

A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

RELATED APPLICATIONS

This Application is a divisional application of U.S. patent applicationSer. No. 10/920,579 filed Aug. 17, 2004, which is a divisionalapplication of Ser. No. 09/143,585 filed Aug. 31, 1998, now U.S. LettersPat. No. 6,781,212 entitled “SELECTIVELY DOPED TRENCH DEVICE ISOLATION”,which are hereby incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor device design andfabrication and more particularly to trench isolation of such devices.

2. Description of the Related Art

In the semiconductor industry, there is a continuing trend towardsincreasing the number of components formed in an area of an integratedcircuit. This trend is resulting in Ultra Large Scale Integration (ULSIdevices). This trend is driving the semiconductor industry to explorenew materials and processes for fabricating integrated devices havingsub-micron sized features so that more devices can be formed in the samearea of an integrated circuit. This is particularly true for themanufacture of the Metal Oxide Semiconductor (MOS) or ComplementaryMetal Oxide Semiconductor (CMOS) Integrated Circuits (ICs).

Such ICs generally consist of an array of active devices such astransistors or capacitors. Typically, each of the capacitors andtransistors are separated by an isolation structure that is adapted toelectrically isolate adjacent active devices from each other. As devicedensity has increased, the overall dimensions of the capacitors,transistors and the isolation structures on a chip have been reduced bythe manufacturers to meet limited space requirements. Moreover, thesedevices are being placed in closer proximity to each other to increasedevice density. This situation presents a special challenge for theisolation structures as these devices must be smaller and yet stillprovide the necessary isolation. In fact, the integrity and thereliability of each active device greatly depends on ability toelectrically isolate each active device from adjacent active devices asleakage currents from adjacent devices can result in failure. Thus,despite decreasing dimensions of isolation structures, each isolationstructure must still maintain the required degree of isolation toprevent leakage currents between the individual active devices.

Active devices on a chip are generally spaced apart by the regions knownas field regions in which the isolation structures are formed. In fact,isolation between the active devices is achieved by interposing theisolation structure, normally called a field device, therebetween tointerrupt the parasitic conduction. In particular, it is understood thata difference in potential between adjacent active devices induces chargecarriers to travel between the two active devices. The difference inpotential is referred to as the threshold voltage required to producethis parasitic conduction.

In many applications, the isolation structure used to inhibit parasiticconduction is formed out of a generally non-conductive oxide material,such as silicon oxide. Preferably, the presence of the isolationstructure increases the threshold voltage necessary to produce parasiticconduction to a point where the difference in potential between adjacentactive devices never reaches the threshold voltage. This thresholdvoltage, in the context of isolation structures, is commonly referred toas the field threshold. With these types of isolation structures, thethreshold voltage resulting from the formation of the isolationstructure is proportionate to the thickness of the isolation structure.Hence, the thicker the structure, the greater the threshold voltagewhich results in less parasitic conduction during active deviceoperation.

For clarity, the mechanism of parasitic conduction between activedevices can be viewed as a parasitic device that is established betweenactive devices. The parasitic device is analogous in operation to afield effect transistor. Consequently, the isolation structure, actingas a gate in a field effect transistor, increases the threshold voltageof the parasitic devices that spontaneously exist between the activedevices and prevents inadvertent electrical coupling between the activedevices. The goal in any isolation scheme, is to make this fieldthreshold voltage as high as possible without adversely effecting thecharacteristics of adjacent devices. In the semiconductor industry, thisis conventionally done by forming thick isolation structures in thefield regions.

Such isolation structures are conventionally formed using processes suchas LOCOS (For LOCalized Oxidation of Silicon) or trench isolation. Inthe LOCOS process, thick isolation structures known as field oxideregions are formed by oxidizing the regions between adjacent activedevices. Although the high field threshold provided by such thick fieldoxide effectively isolates the active devices, the LOCOS processpresents some disadvantages associated with the nature of the oxidationprocess. For example, thick isolation structures formed throughoxidation consume a considerable amount of area on the chip limiting theamount of area available for active devices and thereby limiting theactive device density. Moreover, during the oxidation process there islateral encroachment into the active areas of the chip. This lateralencroachment is known as bird's beak encroachment and it further limitsthe size of the active areas of the chip and the active device density.This bird's beak encroachment remains a significant problem even asdevice dimensions and isolation structure dimensions are decreased toaccommodate higher active device densities.

One alternative to the LOCOS process is known as trench isolation.Advantageously, trench isolation processes do not experience bird's beaklateral encroachment and resulting active area loss. Trench isolationgenerally involves etching a trench in the substrate between the activedevices and filling the trench with an insulator such as silicon oxide.In order to provide high field threshold voltages and to prevent theformation of a conductive channel between neighboring active devices,the trench must have a sufficient depth and width.

However, scaling down trench dimensions to accommodate higher activedevice densities on an integrated circuit adversely affects the fieldthreshold voltage and can result in parasitic conduction between theactive devices. Consequently, while trench isolation techniquesgenerally do not have the lateral encroachment problems associated withLOCOS isolation structures, trench isolation structures must still haverelatively large minimum dimensions to maintain adequate isolationbetween adjacent active devices which inhibits significant increase indevice density on an integrated circuit.

One solution to this problem is to use a channel-stop implant to dopeside walls of the trench so as to further limit the formation of aconductive channel between the active devices. Channel-stop implants areusually the same dopant type as the dopant type of the substrate, butchannel stop implants are implanted in higher doping concentrations toeffectively limit the channel formation. However, doping trench walls isa tedious and technically difficult process, and the doped implant oftenhas a tendency to diffuse into active device regions, resulting inundesirable changes in device characteristics.

One other alternative trench isolation method fills the trench withpolysilicon. In this method device isolation can be achieved by applyinga low bias to the polysilicon so as to prevent channel formation betweenthe active devices. However, as the trench dimensions are reduced, thefield threshold voltage of these isolation structures may not beadequately high enough to prevent channel formation. Moreover, as in thecase of silicon oxide filled trenches, poly filled trenches may stillrequire side wall channel stop implants.

Thus, in semiconductor integrated circuit technologies, there is needfor isolation structures having high field threshold voltages andimproved isolation characteristics so as to provide isolation betweenadjacent active devices in higher active device density applications. Tothis end, there is a need for isolation structures that reducechanneling between adjacent devices but do not require time consumingdoping processes to achieve adequately isolating structures.

SUMMARY OF THE INVENTION

The aforementioned needs are satisfied by the process and device of thepresent invention which is directed to manufacture of a selectivelydoped trench isolation device. In one aspect, the present invention iscomprised of an isolation structure formed in a substrate of asemiconductor material having a first work function, the isolationstructure comprising a trench formed in the substrate with an insolationlayer positioned on the trench surfaces and a material having a secondwork function, different from the first work function, that ispositioned inside of the trench on the exposed surface of the insulatinglayer. In one aspect, the isolation material is of the same dopant typeas the substrate but has a higher dopant concentration. In one aspect,the isolation material is formed of a material that can be biased so asto increase the threshold voltage of the isolation structure.

In another aspect of the invention, a method of forming an isolationstructure is provided. The method is comprised of forming a trench in asubstrate of a first work function, depositing an isolation orinsulating layer on the inner surfaces of the trench and thenpositioning a material having a second work function, different from thefirst work function on the inner surfaces of the isolation or insulatingmaterial. In one embodiment, the isolation material is adapted to form agate that can be biased.

In one embodiment of the present invention, a trench is formed in afield region of a p-type substrate and a thin layer of field oxide isformed on the trench side walls and the floor. The oxide covered trenchis then filled with a material having work function value that is higherthan the work function value of the p-type substrate. In this embodimentthe material is a heavily doped P+ polysilicon material. The higher workfunction of the P+ polysilicon material produces a high flat bandvoltage that produces high threshold voltages. This high thresholdvoltage of the trench isolation device prevents current leakages betweenthe active devices that are separated by the trench isolation device ofthis invention. Further, this threshold voltage can advantageously becontrolled by varying the bias on the gate material. Moreover, in thisembodiment, the dopant atoms from the polysilicon diffuse through theisolation layer thereby forming a higher doped channel stop regionadjacent the interface between the substrate and the isolation regionwithout requiring the use of channel implants or side wall-implants.

These and other objects and advantages of the present invention willbecome more fully apparent from the following description taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view of a silicon substrate having a maskstructure formed on top of the substrate;

FIG. 2 is a schematic view of the structure shown in FIG. 1 wherein alayer of photo resist material has been formed on top of the maskstructure;

FIG. 3 is a schematic view of the structure shown in FIG. 2 wherein themask structure and the silicon substrate have been etched to form atrench in the substrate;

FIG. 4 is a schematic view of the structure shown in FIG. 3 wherein thephoto resist material has been stripped from the mask structure, and asilicon oxide layer is formed on the exposed surfaces of the trench andthe mask structure;

FIG. 5 is a schematic view of the structure shown in FIG. 4 wherein a P+polysilicon layer has been selectively deposited on the silicon oxidelayer to fill the trench;

FIG. 6 is a schematic view of the structure shown in FIG. 5 wherein P+polysilicon layer has been planarized;

FIG. 7 is a schematic view of the structure shown in FIG. 6 wherein agated mask structure has been removed and the P+ poly material has beenfurther planarized to form a gated trench isolation device;

FIG. 8 is a schematic view of the structure shown in FIG. 7 whereintransistors have been formed adjacent the gated trench isolation device;and

FIG. 9A-9C show I-V curves comparing leakage currents of three separateexemplary trench isolation devices.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made to the drawings wherein like numerals referto like parts throughout. FIG. 1 illustrates a semiconductor substrate100 where a mask structure 102 is formed on a top surface 104 of thesubstrate 100. In this embodiment, the semiconductor substrate 100preferably comprises a p-type silicon substrate, and the mask structure102 may be comprised of a silicon oxide layer 106 and a nitride layer108. The silicon oxide layer 106, often referred to as pad-oxide layer,may be formed by oxidation of the top surface 104 using any of a numberof well-known wet or dry oxidation techniques so as to grow a siliconoxide layer with a thickness on the order of approximately 30 to 300Angstroms. The nitride layer 108 may be formed on the pad-oxide layer106 using any of a well-known deposition processes, preferably aChemical Vapor Deposition (CVD) process. The nitride layer maypreferably be deposited to a thickness of approximately 1000-2500 A.

As shown in FIG. 2, following the deposition of the nitride layer 108, aresist layer 110 is formed on the nitride layer 108 through conventionalresist forming techniques. Thereafter, as illustrated in FIG. 3, atrench 112 is formed in the substrate 100 by patterning and defining theresist layer 110, and subsequently etching the masking structure 102 andsubstrate 100 to form the trench 112 within the substrate 100. Thepatterning and definition of the resist layer 110 can be carried outusing any of a well-known conventional photolithographic techniques inthe art.

More particularly, a selective etch process may initially be used toetch an aperture 114, which has side walls 116, through the maskstructure 102. The trench 112 is then etched in the substrate throughthe aperture 114. Etching of the substrate 100 continues until a floor118 of the trench 112 is horizontally formed at a selected depth withinthe substrate 100, while side walls 120 of the trench 112 extendgenerally vertically downwardly from the interface between the substrate100 and the mask structure 102. Etching of the mask structure 102 andthe substrate 100 may be performed using a dry etch technique, such as aReactive Ion Etching (RTE) technique, in a manner well known in the artof semiconductor processing so that the trench 112 is formed withgenerally vertical sidewalls 120.

As illustrated in FIG. 4, the resist layer 110 is then removed from thetop of the nitride layer 108. Subsequently, a layer 122 of a firstmaterial may be formed on the floor 118 and the side walls 120 of thetrench 112 as well as side walls 116 and the top of the nitride layer108. In this embodiment, the first material layer 122 comprises anisolation material layer and is preferably a silicon oxide layer. Aswill be described further hereinbelow, the silicon oxide layer 122 formsthe field oxide layer of the gated trench isolation device of thisembodiment. The silicon oxide layer 122 may be formed using either awell known a deposition or a well known oxidation technique to athickness range of approximately 50-500 Å depending upon the technologyand chip operating voltage.

As illustrated in FIG. 4, a second material 124 is deposited on thefield oxide layer 122 so as to fill trench 112, aperture 114 and tocover the top surface of the nitride layer 108. As will also bedescribed further hereinbelow, the second material 124 is connected tothe contact element or the gate of the field isolation device of thisembodiment.

In this embodiment, the second material 124 preferably comprises amaterial having a work function value that is higher than the workfunction value of the material forming the substrate 100 (p-typeimpurity doped silicon). As is well known to those skilled in thesemiconductor art, the work function is a specific material parameterwhich may be defined as a threshold energy required to remove anelectron from a material. In one embodiment, the second material 124 maycomprise a selectively heavily p-type impurity doped polysilicon (P+poly) material having a work function value of approximately 5.2electron volts. In this embodiment, the P+ poly material comprisespolysilicon with a p-type doping impurity introduced therein, preferablyBoron with a preferred doping concentration range of approximately10¹⁹-10²¹ atoms cm⁻³. The second material 124 is used in conjunctionwith a p-type silicon substrate 100 having a doping concentration ofapproximately 10¹⁴-10¹⁵ atoms cm⁻³ and a work function of approximately4.9 electron volts. Alternatively, as will be discussed below, thesecond material 124 can also be an n-type impurity doped polysiliconmaterial (N+ poly). This IN+ poly has a work function value of 4.17electron volts.

As illustrated in FIGS. 6-7, once the second material 124 is depositedon the field oxide layer 122, the second material 124 is then planarizeddown to the level of a portion of the oxide layer 122 which is on top ofthe nitride layer 108. A chemical mechanical polishing (CMP) process maypreferably be used to planarize the second material 124. Alternatively,however, a dry etch process may also be used to remove this secondmaterial layer. As shown in FIG. 7, the second material 124 is thenfurther planarized down to the level of the first surface 104 of thesubstrate 100 preferably removing the nitride layer 108 and the padoxide 106 so as to reveal the adjacent active areas 126 a, 126 b and anembodiment of a field isolation device 127 interposed therebetween. Thefield isolation device 127 has the field oxide layer 122 and the secondmaterial 124.

As an alternative to using CMP to remove the masking stack 108 and thepad oxide 106, the second material may be selectively dry etched down tothe level of the active areas 126 a, 126 b while the remaining portionsof the mask structure 108 protects underlying active areas 105 frombeing etched. After this etching is complete, the mask structure 108 andthe exposed portions of the field oxide layer 122 are removed usingsuitable dry or wet etch processes.

Hence, the process results in the formation of the isolation structure127 having the oxide layer 122 on each of the inner surfaces of thetrench 112 and the second material 124 positioned inside of the oxidelayers 122. As discussed above, the P+ poly material comprises a highwork function material when compared to the material of the substrate100 while the N+ poly material comprises a low work function materialwhen compared to the material of the substrate 100. Hence, the fieldisolation device 127 is comprised of a isolation material that ispositioned within a trench so as to be interposed between two materials(e.g., P+ poly and the substrate) having positively different workfunctions or two materials (e.g., N+ poly and the substrate) havingnegatively different work function.

It is known that, for a MOS gate structure, the work function differencebetween a metal (or polysilicon) and semiconductor, which both areconnected through an oxide interlayer so as to form ametal-oxide-semiconductor structure, is generally defined as the flatband voltage of that structure. The flat band voltage is a well-knownconcept to those skilled in the semiconductor art. It is further knownin the art that, in a MOS gate structure, the threshold voltage is astrong function of a flat band voltage. A positively different workfunction between the P+ poly and the p-doped substrate results in alarger threshold voltage than that of a negatively different workfunction.

Consequently, it will be appreciated that the field isolation device 127has an increased field threshold voltage as a result of using materialsto form the isolation structure that has a positive work functiondifference from the material forming the substrate. As previouslymentioned, field threshold voltage is the voltage at which aninadvertent current flow (leakage) between the active devices may occur.Thus, the higher the field threshold voltage is, the less likely therewill be a leakage current between adjacent active devices. In thisembodiment, the resulting high work function difference between thep-doped substrate 100 and the P+ poly material advantageously increasesfield threshold voltage of the isolation structure thereby preventingshortages between the adjacent devices.

Moreover, as illustrated in FIG. 5, doping implant in the heavily dopedsecond material 124 will diffuse through the field oxide layer 122 tocreate a dopant impurity rich region 125 at the interface between thesubstrate 100 and the field oxide layer 122. This dopant rich region 125acts like a channel stop region further increasing the field thresholdvoltage and inhibiting leakage across the isolation device 127. Asdiscussed, a channel-stop region further enhances the field thresholdvoltage and inhibits parasitic conduction. Hence, the process of thepreferred embodiment results in the creation of channel stop implantsadjacent the side walls of the isolation device 127 without requiringthe use of tedious and expensive channel stop implant techniques.Consequently, the field isolation device 127 of this embodiment may havea field threshold voltage of at least 10 volts.

As illustrated in FIG. 8, following the formation of the field isolationdevice 127, a pair of exemplary transistors (MOSFETS), namely the firsttransistor 128 and the second transistor 130, may be formed on theeither side of the field isolation device 127. In the illustratedembodiment, a contact element 131 is connected to the second material124 of the field device 127 so that a bias voltage can be applied to thesecond material 124. However, the contact element can be replaced with aconventional gate structure (not shown) which generally comprises alayer of gate oxide deposited on the second material, and a polysiliconlayer deposited on the gate oxide layer. As shown in FIG. 8, the firsttransistor 128 comprises a gate oxide layer 132 a located between a gateelectrode 132 a and a channel region 136 a. The transistor 128 also havea source and drain regions 138 a and 140 a which may be formed as dopeddiffused regions as in the manner shown in FIG. 8. Similarly, the secondtransistor 130 has a gate oxide layer 132 b, a gate electrode 132 b, achannel region 136 b as well as source and drain regions 138 b and 140b. The transistors 128 and 130 are formed using methods which arewell-known in the semiconductor device manufacturing technologies.

As explained above, when P+ poly is used as the second material 124, dueto the positive work function difference between the P+ poly materialand the p-type substrate 100 and resulting high flat band voltage, thefield isolation device 127 introduces higher threshold voltages and thusprevents current leakages between the transistors 128 and 130. Further,this threshold voltage can advantageously be controlled by varying thebias on the second material 124.

Experimentally, doped polysilicon isolation structures exhibit superiorleakage characteristics compared to that of a silicon oxide (SiO₂)isolation device of the prior art when these devices are tested at anisolation scheme that is similar to one shown in FIG. 8. For example,FIG. 9A-9C are current-voltage characteristics for three NMOS trenchisolation devices having trench depth of 0.3 μm, junction depth of 0.2μm and V_(bs)=−1 Volt (bulk to substrate voltage), a trench width of 1μm, and a given trench length common for each device (0.21 μm in thiscase). The isolation structures can be modeled as a transistor with theisolation device forming a gate and the two active areas forming a drainand a source. Under quiescent conditions (V_(gs)=0 volts and V_(ds)=10Volts), the resulting punchthrough current leakages (current leakagesfrom the trench isolation test devices) are indicated on current-voltagecurves shown in FIGS. (9A-9B). As shown by curve 142 in FIG. 9A, for thesilicon oxide filled trench isolation device of the prior art (i.e., thetrench is etched in the substrate and filled with SiO₂), thepunchthrough leakage current corresponds to 4.3 E-10 Amperes/trenchwidth (μm) under above given conditions. This undesirably high leakageis due to varying surface potential along the SiO₂-substrate interfaceregion so that when the device is biased at 0 volts, the potential onthis interface, or channel, is not always 0 volts. In such devices, nearthe drain region, this surface potential is generally greater than zero,thus causing a leakage current from the drain side.

As shown by the curve 144 in FIG. 9B, for an N+ poly filled trenchdevice, this leakage current is approximately reduced three orders ofmagnitude down to 4.1 E-13 Amperes μm (current/trench width). As notedabove, an N+ poly filled trench device can be formed with the sameprocess used for forming a P+ poly filled device (i.e., there is an SiO₂layer between the N+ poly and the substrate). However, differing fromthe SiO₂ filled trench, when the N+ poly is biased at 0 volts, thepotential along the SiO₂-substrate interface region, or channel, isalmost 0 volts. This, in turn, significantly reduces the leakagecurrents.

As shown in FIG. 9C by the curve 146, for the trench isolation deviceincorporating a P+ poly filled trench, this leakage current is at least5 or more orders of magnitude lower than the current leakage thatoccurred in the prior art trench oxide device down to approximately 6.5E-15 Amperes μm (current/trench width). These results are taken to berepresentative of the isolation device of the present invention, andresults represented herein further demonstrates the superior isolationcharacteristics of the field isolation device of the present invention.

Although the unique aspects of the preferred embodiment are disclosed inconnection with n-channel metal-oxide-semiconductor (NMOS) ICtechnology, the same inventive aspects can also be applied to thep-channel metal-oxide-semiconductor (PMOS) technology, the complementarymetal-oxide-semiconductor (CMOS) technology and themetal-oxide-semiconductor (MOS) memory technologies without departingfrom the spirit of the present invention.

Although the foregoing invention has been described in terms of certainpreferred embodiments, other embodiments will become apparent to thoseof ordinary skill in the art, in view of the disclosure herein.Accordingly, the present invention is not intended to be limited by therecitation of preferred embodiments, but is instead intended to bedefined solely by reference to the appended claims.

1. A method of forming an isolation device on a field region of asubstrate comprising: forming a trench in the substrate wherein saidtrench defines a trench surface; forming a first material layer on saidsurface wherein said first material is comprised of an insulatingmaterial; filling said trench with a second material having a workfunction value higher than the work function value of the substrate; andapplying an electrical bias on said second material so as to induce afield threshold voltage into said field region wherein said fieldthreshold voltage inhibits electrical conduction in that field region.2. The method of claim 1, further comprising forming a mask structure onsaid substrate prior to forming said trench step.
 3. The method of claim2, further comprising patterning and etching said masking structure. 4.The method of claim 2, wherein the act of forming a mask structurecomprises: forming a silicon oxide layer on said substrate; anddepositing a nitride layer on said silicon oxide layer.
 5. The method ofclaim 1, wherein said forming a first material layer on said surfacecomprises growing an silicon oxide layer on said surface.
 6. The methodof claim 1, wherein the act of said filling said trench comprisesselectively depositing a P+ polysilicon material on said silicon oxidelayer wherein said P+ polysilicon material comprises a p-type dopantmaterial having a concentration range of 10¹⁹-10²¹ atoms cm⁻³.
 7. Themethod of claim 6, wherein the act of selectively depositing a P+polysilicon material on said silicon oxide results in forming a channelstop layer between the side walls of said trench and said silicon oxidelayer by diffusion of said dopant material into an interface between theside walls of said trench and said silicon oxide layer.
 8. Asemiconductor integrated circuit comprising; a semiconductor substratehaving a first work function value, said substrate defines a firstactive area having a first active device and a second active area havinga second active device; and an isolation structure which includes atrench formed in said substrate between said first and second activeareas and further includes an insulating layer positioned on the sidewalls of said trench and a second material filling said trench so thatsaid insulating layer is interposed between the substrate and the secondmaterial wherein said second material comprises a material having asecond work function value which is greater than the first work functionvalue of said substrate.
 9. The semiconductor integrated circuit ofclaim 8, wherein said substrate is a p-type silicon substrate.
 10. Thesemiconductor integrated circuit of claim 8, wherein said first workfunction value is approximately 4.9 electron volts.
 11. Thesemiconductor integrated circuit of claim 8, wherein said second workfunction value is approximately 5.2 electron volts.
 12. Thesemiconductor integrated circuit of claim 8, wherein said insulatinglayer comprises silicon dioxide (SiO₂).
 13. The semiconductor integratedcircuit of claim 8, wherein said second material is comprised of P+polysilicon material, said P+ polysilicon material comprises a dopantmaterial with a concentration range of 10¹⁹-10²¹ atoms cm⁻³.
 14. Thesemiconductor integrated circuit of claim 13, wherein said dopantmaterial is boron.
 15. The semiconductor integrated circuit of claim 13,wherein a channel stop layer is formed at an interface between saidtrench surface and said insulating layer as a result of diffusion ofdopant materials from said P+ polysilicon material into said substrate.16. The semiconductor integrated circuit of claim 15, wherein the workfunction difference between the silicon substrate and the P+ polysiliconmaterial induces a threshold voltage sufficient to prevent electricalconduction between said active devices.